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? semiconductor components industries, llc, 2001 february, 2001 rev. 7 1 publication order number: mc14536b/d mc14536b programmable timer the mc14536b programmable timer is a 24stage binary ripple counter with 16 stages selectable by a binary code. provisions for an onchip rc oscillator or an external clock are provided. an onchip monostable circuit incorporating a pulsetype output has been included. by selecting the appropriate counter stage in conjunction with the appropriate input clock frequency, a variety of timing can be achieved. ? 24 flipflop stages e will count from 2 0 to 2 24 ? last 16 stages selectable by fourbit select code ? 8bypass input allows bypassing of first eight stages ? set and reset inputs ? clock inhibit and oscillator inhibit inputs ? onchip rc oscillator provisions ? onchip monostable output provisions ? clock conditioning circuit permits operation with very long rise and fall times ? test mode allows fast test sequence ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 3.) 500 mw t a operating temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14536bcp pdip16 2000/box mc14536bdw soic16 47/rail marking diagrams 1 16 pdip16 p suffix case 648 mc14536bcp awlyyww mc14536bdwr2 soic16 1000/tape & reel soic16 dw suffix case 751g 1 16 14536b awlyyww 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. soeiaj16 f suffix case 966 1 16 mc14536b alyw mc14536bf soeiaj16 see note 1.
mc14536b http://onsemi.com 2 stages 9 thru 24 q 24 q 23 q 22 q 21 q 20 q 19 q 18 q 17 q 16 q 15 q 14 q 13 q 12 q 11 q 10 q 9 decoder monostable multivibrator decode out 13 mono-in15 d12 c11 b10 a9 v dd = pin 16 v ss = pin 8 stages 1 thru 8 8 bypass set reset clock inh. 7216 5 out 2 4 out 1 3 in 1 osc. inhibit14 figure 1. pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 d decode osc inh mono-in v dd a b c out 1 in 1 reset set v ss clock inh 8-bypass out 2 figure 2. block diagram
mc14536b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (note 4.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) pins 4 & 5 (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 1.2 0.25 0.62 1.8 e e e e 1.0 0.25 0.5 1.5 1.7 0.36 0.9 3.5 e e e e 0.7 0.14 0.35 1.1 e e e e madc (v oh = 2.5 vdc) source (v oh = 4.6 vdc) pin 13 (v oh = 9.5 vdc) (v oh = 13.5 vdc) 5.0 5.0 10 15 3.0 0.64 1.6 4.2 e e e e 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 e e e e 1.7 0.36 0.9 2.4 e e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.010 0.020 0.030 5.0 10 20 e e e 150 300 600 m adc total supply current ( note 5., 6.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (1.50 m a/khz) f + i dd i t = (2.30 m a/khz) f + i dd i t = (3.55 m a/khz) f + i dd m adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.003.
mc14536b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (note 7.) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (note 8.) max unit output rise and fall time (pin 13) t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 e e e 100 50 40 200 100 80 ns propagation delay time clock to q1, 8bypass (pin 6) high t plh , t phl = (1.7 ns/pf) c l + 1715 ns t plh , t phl = (0.66 ns/pf) c l + 617 ns t plh , t phl = (0.5 ns/pf) c l + 425 ns t plh , t phl 5.0 10 15 e e e 1800 650 450 3600 1300 1000 ns clock to q1, 8bypass (pin 6) low t plh , t phl = (1.7 ns/pf) c l + 3715 ns t plh , t phl = (0.66 ns/pf) c l + 1467 ns t plh , t phl = (0.5 ns/pf) c l + 1075 ns t plh , t phl 5.0 10 15 e e e 3.8 1.5 1.1 7.6 3.0 2.3 m s clock to q16 t phl , t plh = (1.7 ns/pf) c l + 6915 ns t phl , t plh = (0.66 ns/pf) c l + 2967 ns t phl , t plh = (0.5 ns/pf) c l + 2175 ns t plh , t phl 5.0 10 15 e e e 7.0 3.0 2.2 14 6.0 4.5 m s reset to q n t phl = (1.7 ns/pf) c l + 1415 ns t phl = (0.66 ns/pf) c l + 567 ns t phl = (0.5 ns/pf) c l + 425 ns t phl 5.0 10 15 e e e 1500 600 450 3000 1200 900 ns clock pulse width t wh 5.0 10 15 600 200 170 300 100 85 e e e ns clock pulse frequency (50% duty cycle) f cl 5.0 10 15 e e e 1.2 3.0 5.0 0.4 1.5 2.0 mhz clock rise and fall time t tlh , t thl 5.0 10 15 no limit e reset pulse width t wh 5.0 10 15 1000 400 300 500 200 150 e e e ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance.
mc14536b http://onsemi.com 5 pin descriptions inputs set (pin 1) e a high on set asynchronously forces decode out to a high level. this is accomplished by setting an output conditioning latch to a high level while at the same time resetting the 24 flipflop stages. after set goes low (inactive), the occurrence of the first negative clock transition on in 1 causes decode out to go low. the counter's flipflop stages begin counting on the second negative clock transition of in 1 . when set is high, the onchip rc oscillator is disabled. this allows for very lowpower standby operation. reset (pin 2) e a high on reset asynchronously forces decode out to a low level; all 24 flipflop stages are also reset to a low level. like the set input, reset disables the onchip rc oscillator for standby operation. in 1 (pin 3) e the device's internal counters advance on the negativegoing edge of this input. in 1 may be used as an external clock input or used in conjunction with out 1 and out 2 to form an rc oscillator. when an external clock is used, both out 1 and out 2 may be left unconnected or used to drive 1 lsttl or several cmos loads. 8bypass (pin 6) e a high on this input causes the first 8 flipflop stages to be bypassed. this device essentially becomes a 16stage counter with all 16 stages selectable. selection is accomplished by the a, b, c, and d inputs. (see the truth tables.) clock inhibit (pin 7) e a high on this input disconnects the first counter stage from the clocking source. this holds the present count and inhibits further counting. however, the clocking source may continue to run. therefore, when clock inhibit is brought low, no oscillator startup time is required. when clock inhibit is low, the counter will start counting on the occurrence of the first negative edge of the clocking source at in 1 . osc inhibit (pin 14) e a high level on this pin stops the rc oscillator which allows for very lowpower standby operation. may also be used, in conjunction with an external clock, with essentially the same results as the clock inhibit input. monoin (pin 15) e used as the timing pin for the onchip monostable multivibrator. if the monoin input is connected to v ss , the monostable circuit is disabled, and decode out is directly connected to the selected q output. the monostable circuit is enabled if a resistor is connected between monoin and v dd . this resistor and the device's internal capacitance will determine the minimum output pulse widths. with the addition of an external capacitor to v ss , the pulse width range may be extended. for reliable operation the resistor value should be limited to the range of 5 k w to 100 k w and the capacitor value should be limited to a maximum of 1000 pf. (see figures 3, 4, 5, and 10). a, b, c, d (pins 9, 10, 11, 12) e these inputs select the flipflop stage to be connected to decode out. (see the truth tables.) outputs out 1 , out 2 (pin 4, 5) e outputs used in conjunction with in 1 to form an rc oscillator. these outputs are buffered and may be used for 2 0 frequency division of an external clock. decode out (pin 13) e output function depends on configuration. when the monostable circuit is disabled, this output is a 50% duty cycle square wave during free run. test mode the test mode configuration divides the 24 flipflop stages into three 8stage sections to facilitate a fast test sequence. the test mode is enabled when 8bypass, set and reset are at a high level. (see figure 8.)
mc14536b http://onsemi.com 6 truth tables input stage selected 8bypass d c b a stage selected for decode out 0 0 0 0 0 9 0 0 0 0 1 10 0 0 0 1 0 11 0 0 0 1 1 12 0 0 1 0 0 13 0 0 1 0 1 14 0 0 1 1 0 15 0 0 1 1 1 16 0 1 0 0 0 17 0 1 0 0 1 18 0 1 0 1 0 19 0 1 0 1 1 20 0 1 1 0 0 21 0 1 1 0 1 22 0 1 1 1 0 23 0 1 1 1 1 24 input stage selected 8bypass d c b a stage selected for decode out 1 0 0 0 0 1 1 0 0 0 1 2 1 0 0 1 0 3 1 0 0 1 1 4 1 0 1 0 0 5 1 0 1 0 1 6 1 0 1 1 0 7 1 0 1 1 1 8 1 1 0 0 0 9 1 1 0 0 1 10 1 1 0 1 0 11 1 1 0 1 1 12 1 1 1 0 0 13 1 1 1 0 1 14 1 1 1 1 0 15 1 1 1 1 1 16 function table in 1 set reset clock inh osc inh out 1 out 2 decode out 0 0 0 0 no change 0 0 0 0 advance to next state x 1 0 0 0 0 1 1 x 0 1 0 0 0 1 0 x 0 0 1 0 e e no change x 0 0 0 1 0 1 no change 0 0 0 0 x 0 1 no change 1 0 0 0 advance to next state x = don't care
mc14536b http://onsemi.com 7 logic diagram stages 18 thru 23 24 17 stages 10 thru 15 16 t 9 stages 2 thru 7 8 t 1 6 2 reset 8-bypass 14 osc inhibit 3 in 1 4 out 1 out 2 5 set 1 7 clock inhibit r en c s q a9 b10 c11 d12 decoder decoder out 13 15 mono-in v dd = pin 16 v ss = pin 8
mc14536b http://onsemi.com 8 figure 1. rc oscillator stability figure 2. rc oscillator frequency as a function of r tc and c r s = 0, f = 10.15 khz @ v dd = 10 v, t a = 25 c r s = 120 k w , f = 7.8 khz @ v dd = 10 v, t a = 25 c r tc = 56 k w , c = 1000 pf v dd = 15 v 10 v 5.0 v 8.0 4.0 0 -4.0 -8.0 -12 -16 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c)* *device only. frequency deviation (%) typical rc oscillator characteristics (for circuit diagram see figure 11 in application) 100 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 1.0 k 10 k 100 k 1.0 m 0.0001 0.001 0.01 0.1 r tc , resistance (ohms) c, capacitance ( m f) f, oscillator frequency (khz) f as a function of c (r tc = 56 k w ) (r s = 120 k) f as a function of r tc (c = 1000 pf) (r s 2r tc ) v dd = 10 v figure 3. typical c x versus pulse width @ v dd = 5.0 v figure 4. typical c x versus pulse width @ v dd = 10 v 100 0.1 1.0 10 1000 100 10 1.0 c x , external capacitance (pf) , pulse width ( t w m s) r x = 100 k w 50 k w 10 k w 5 k w t a = 25 c v dd = 5 v formula for calculating t w in microseconds is as follows: t w = 0.00247 r x ? c x 0.85 where r is in k w , c x in pf. 1000 100 10 1.0 c x , external capacitance (pf) 100 0.1 1.0 10 , pulse width ( t w m s) formula for calculating t w in microseconds is as follows: t w = 0.00247 r x ? c x 0.85 where r is in k w , c x in pf. r x = 100 k w 50 k w 10 k w 5 k w t a = 25 c v dd = 10 v figure 5. typical c x versus pulse width @ v dd = 15 v 1000 100 10 1.0 c x , external capacitance (pf) 100 0.1 1.0 10 , pulse width ( t w m s) formula for calculating t w in microseconds is as follows: t w = 0.00247 r x ? c x 0.85 where r is in k w , c x in pf. r x = 100 k w 50 k w 10 k w 5 k w t a = 25 c v dd = 15 v monostable characteristics (for circuit diagram see figure 10 in application)
mc14536b http://onsemi.com 9 figure 6. power dissipation test circuit and waveform figure 7. switching time test circuit and waveforms v dd 0.01 m f ceramic 500 m f i d c l c l c l v ss pulse generator set reset 8-bypass in 1 c inh mono-in osc inh c b a d out 1 out 2 decode out 20 ns 20 ns 90% 10% 50% 50% duty cycle pulse generator set reset 8-bypass in 1 c inh mono-in osc inh c b a d out 1 out 2 decode out c l v ss v dd 20 ns 20 ns 50% in 1 t wl t wh 50% t phl 90% 10% t plh t tlh t thl out functional test sequence test function (figure 8) has been included for the reduction of test time required to exercise all 24 counter stages. this test function divides the counter into three 8stage sections and 255 counts are loaded in each of the 8stage sections in parallel. all flipflops are now at a a1o. the counter is now returned to the normal 24stages in series configuration. one more pulse is entered into in 1 which will cause the counter to ripple from an all a1o state to an all a0o state. figure 8. functional test circuit v dd v ss pulse generator set reset 8-bypass in 1 c inh mono-in osc inh c b a d out 1 out 2 decode out
mc14536b http://onsemi.com 10 functional test sequence inputs outputs comments in 1 set reset 8bypass decade out q1 thru q24 all 24 stages are in reset mode. 1 0 1 1 0 all 24 stages are in reset mode . 1 1 1 1 0 counter is in three 8 stage sections in parallel mode. 0 1 1 1 0 first a1o to a0o transition of clock. 1 0 e e e 1 1 1 255 a1o to a0o transitions are clocked in the counter. 0 1 1 1 1 the 255 a1o to a0o transition. 0 0 0 0 1 counter converted back to 24 stages in series mode. set and reset must be connected together and simultaneously go from a1o to a0o. 1 0 0 0 1 in 1 switches to a a1o. 0 0 0 0 0 counter ripples from an all a1o state to an all a0o state.
mc14536b http://onsemi.com 11 note: when power is first applied to the device, decode out can be either at a high or low state. on the rising edge of a set pulse the output goes high if initially at a low state. the output remains high if initially at a high state. because clock inh is held high, the clock source on the input pin has no effect on the output. once clock inh is taken low, the output goes low on the first negative clock transition. the output returns high depending on the 8by- pass, a, b, c, and d inputs, and the clock input period. a 2 n frequency division (where n = the number of stages selected from the truth table) is obtainable at decode out. a 2 0 divided output of in 1 can be obtained at out 1 and out 2 . figure 9. time interval configuration using an external clock, set, and clock inhibit functions (divideby2 configured) pulse gen. pulse gen. clock 8-bypass a b c d reset osc inh mono-in set clock inh in 1 v ss decode out out 2 out 1 8 16 +v 6 9 10 11 12 2 14 15 1 7 313 5 4 decode out clock inh set in 1 power up v dd
mc14536b http://onsemi.com 12 figure 10. time interval configuration using an external clock, reset, and output monostable to achieve a pulse output (divideby4 configured) note: when power is first applied to the device with the reset input going high, decode out initializes low. bringing the reset input low enables the chip's internal counters. after reset goes low, the 2 n /2 negative transition of the clock input causes decode out to go high. since the monoin input is being used, the output becomes monostable. the pulse width of the output is dependent on the external timing components. the second and all subsequent pulses occur at 2 n x (the clock period) intervals where n = the number of stages selected from the truth table. pulse gen. clock 8-bypass a b c d reset set clock inh mono-in osc inh in 1 v ss decode out out 2 out 1 8 16 +v 6 9 10 11 12 2 1 7 15 14 313 5 4 decode out reset in 1 power up v dd r x c x *t w .00247 ? r x ? c x 0.85 t w in m sec r x in k w c x in pf *t w
mc14536b http://onsemi.com 13 figure 11. time interval configuration using onchip rc oscillator and reset input to initiate time interval (divideby2 configured) note: this circuit is designed to use the onchip oscillation function. the oscillator frequency is deter- mined by the external r and c components. when power is first applied to the device, decode out initializes to a high state. because this output is tied directly to the osc inh input, the oscillator is disabled. this puts the device in a lowcurrent standby condition. the rising edge of the reset pulse will cause the output to go low. this in turn causes osc inh to go low. however, while reset is high, the oscillator is still disabled (i.e.: standby condition). after reset goes low, the output re- mains low for 2 n /2 of the oscillator's period. after the part times out, the output again goes high. pulse gen. 8-bypass a b c d reset osc inh mono-in set clock inh in 1 v ss decode out out 2 out 1 8 16 +v 6 9 10 11 12 2 14 15 1 7 313 5 4 v dd r s r tc c out 2 out 1 reset power up r s f r c decode out t w r tc = hz = ohms = farads f osc 1 2.3r tc c
mc14536b http://onsemi.com 14 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic16 dw suffix plastic soic package case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7
mc14536b http://onsemi.com 15 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o
mc14536b http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14536b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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